Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Synthesis Attributes in Verilog-1995

You must use Verilog-1995 comment-embedded attributes as a suffix to the declaration of an item and must appear before a semicolon, when a semicolon is necessary.

Note: You cannot use the open one-line comment in Verilog HDL when a semicolon is necessary after the line, because it is not clear to which HDL element that the attribute applies. For example, you cannot make an attribute assignment such as reg r; // synthesis <attribute> because the Quartus® Prime software could read the attribute as part of the next line.

Specifying Synthesis Attributes in Verilog-1995

The following show an example of specifying synthesis attributes in Verilog-1995:

// synthesis <attribute> [ = <value> ]
/* synthesis <attribute> [ = <value> ] */

Applying Multiple Attributes to the Same Instance in Verilog-1995

To apply multiple attributes to the same instance in Verilog-1995, separate the attributes with spaces.

//synthesis <attribute1> [ = <value> ] <attribute2> [ = <value> ]

For example, to set the maxfan attribute to 16 and set the preserve attribute on a register called my_reg, use the following syntax:

reg my_reg /* synthesis maxfan = 16 preserve */;