Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Synopsys Design Constraint Files for the Timing Analyzer in Design Partition Scripts

After you have compiled a design using Timing Analyzer constraints, and the timing assignments option is turned on in the scripts, a separate Tcl script is generated to create an .sdc file for each lower-level project. This script includes only clock constraints and minimum and maximum delay settings for the Timing Analyzer.
Note: PLL settings and timing exceptions are not passed to lower-level designs in the scripts.