- 188.8.131.52. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 184.108.40.206. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.3. Auto Gated Clock Conversion
Clock gating is a common optimization technique in ASIC designs to minimize power consumption. You can use the Auto Gated Clock Conversion logic option to optimize your prototype ASIC designs by converting gated clocks into clock enables when you use FPGAs in your ASIC prototyping. The automatic conversion of gated clocks to clock enables is more efficient than manually modifying source code. The Auto Gated Clock Conversion logic option automatically converts qualified gated clocks (base clocks as defined in the Synopsys Design Constraints [SDC]) to clock enables. Click Assignments Settings Compiler Settings Advanced Settings (Synthesis) to enable Auto Gated Clock Conversion.
The gated clock conversion occurs when all these conditions are met:
- Only one base clock drives a gated-clock
- For one set of gating input values, the value output of the gated clock remains constant and does not change as the base clock changes
- For one value of the base clock, changes in the gating inputs do not change the value output for the gated clock
The option supports combinational gates in clock gating network.
The Info tab in the Messages window lists all the converted gated clocks. You can view a list of converted and nonconverted gated clocks from the Compilation Report under the Optimization Results of the Analysis & Synthesis Report. The Gated Clock Conversion Details table lists the reasons for nonconverted gated clocks.
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