Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

4.7. Reducing Compilation Time Revision History

Date Version Changes
2016.05.02 16.0.0
  • Corrected typo in Using Parallel Compilation with Multiple Processors.
  • Stated limitations about deprecated physical synthesis options.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus® Prime .
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Added information about Rapid Recompile feature.



Added restriction about smart compilation in Arria 10 devices.

June 2014 14.0.0 Updated format.
May 2013 13.0.0 Removed the “Limit to One Fitting Attempt”, “Using Early Timing Estimation”, “Final Placement Optimizations”, and “Using Rapid Recompile” sections.

Updated “Placement Effort Multiplier Settings” section.

Updated “Identifying Routing Congestion in the Chip Planner” section.

General editorial changes throughout the chapter.

June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Updated “Using Parallel Compilation with Multiple Processors”.
  • Updated “Identifying Routing Congestion in the Chip Planner”.
  • General editorial changes throughout the chapter.
December 2010 10.1.0
  • Template update.
  • Added details about peak and average interconnect usage.
  • Added new section “Reducing Static Timing Analysis Time”.
  • Minor changes throughout chapter.
July 2010 10.0.0 Initial release.