Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Distributing the Top-Level Quartus® Prime Project

There are several methods that the project lead can use to distribute the “skeleton” or top-level project framework to other partition designers or IP providers.
  • If partition designers have access to the top-level project framework, the project will already include all the settings and constraints needed for the design. This framework should include PLLs and other interface logic if this information is important to optimize partitions.
    • If designers are part of the same design environment, they can check out the required project files from the same source control system. This is the recommended way to share a set of project files.
    • Otherwise, the project lead can provide a copy of the top-level project framework so that each design develops their partition within the same project framework.
  • If a partition designer does not have access to the top-level project framework, the project lead can give the partition designer a Tcl script or other documentation to create the separate Quartus® Prime project and all the assignments from the top-level design.

If the partition designers provide the project lead with a post-synthesis .qxp and fitting is performed in the top-level design, integrating the design partitions should be quite easy. If you plan to develop a partition in a separate Quartus® Prime project and integrate the optimized post-fitting results into the top-level design, use the following guidelines to improve the integration process:

  • Ensure that a LogicLock region constrains the partition placement and uses only the resources allocated by the project lead.
  • Ensure that you know which clocks should be allocated to global routing resources so that there are no resource conflicts in the top-level design.
    • Set the Global Signal assignment to On for the high fan-out signals that should be routed on global routing lines.
    • To avoid other signals being placed on global routing lines, turn off Auto Global Clock and Auto Global Register Controls under More Settings on the Fitter page in the Settings dialog box. Alternatively, you can set the Global Signal assignment to Off for signals that should not be placed on global routing lines.

      Placement for LABs depends on whether the inputs to the logic cells within the LAB use a global clock. You may encounter problems if signals do not use global lines in the partition, but use global routing in the top-level design.

  • Use the Virtual Pin assignment to indicate pins of a partition that do not drive pins in the top-level design. This is critical when a partition has more output ports than the number of pins available in the target device. Using virtual pins also helps optimize cross-partition paths for a complete design by enabling you to provide more information about the partition ports, such as location and timing assignments.
  • When partitions are compiled independently without any information about each other, you might need to provide more information about the timing paths that may be affected by other partitions in the top-level design. You can apply location assignments for each pin to indicate the port location after incorporation in the top-level design. You can also apply timing assignments to the I/O ports of the partition to perform timing budgeting.