Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.22. Maximum Fan-Out

This Maximum Fan-Out attribute and logic option direct the Compiler to control the number of destinations that a node feeds. The Compiler duplicates a node and splits its fan-out until the individual fan-out of each copy falls below the maximum fan-out restriction. You can apply this option to a register or a logic cell buffer, or to a design entity that contains these elements. You can use this option to reduce the load of critical signals, which can improve performance. You can use the option to instruct the Compiler to duplicate a register that feeds nodes in different locations on the target device. Duplicating the register can enable the Fitter to place these new registers closer to their destination logic to minimize routing delay.

To turn off the option for a given node if you set the option at a higher level of the design hierarchy, in the Netlist Optimizations logic option, select Never Allow. If not disabled by the Netlist Optimizations option, the Compiler acknowledges the maximum fan-out constraint as long as the following conditions are met:

  • The node is not part of a cascade, carry, or register cascade chain.
  • The node does not feed itself.
  • The node feeds other logic cells, DSP blocks, RAM blocks, and pins through data, address, clock enable, and other ports, but not through any asynchronous control ports (such as asynchronous clear).

The Compiler does not create duplicate nodes in these cases, because there is no clear way to duplicate the node, or to avoid the small differences in timing which could produce functional differences in the implementation (in the third condition above in which asynchronous control signals are involved). If you cannot apply the constraint because you do not meet one of these conditions, the Compiler issues a message to indicate that the Compiler ignores the maximum fan-out assignment. To instruct the Compiler not to check node destinations for possible problems such as the third condition, you can set the Netlist Optimizations logic option to Always Allow for a given node.

Note: If you have enabled any of the Quartus® Prime netlist optimizations that affect registers, add the preserve attribute to any registers to which you have set a maxfan attribute. The preserve attribute ensures that the netlist optimization algorithms, such as register retiming, do not affect the registers.

You can set the Maximum Fan-Out logic option in the Quartus® Prime software. This option supports wildcard characters. You can also set the maxfan attribute in your HDL code, as shown in these examples. In these examples, the Compiler duplicates the clk_gen register, so its fan-out is not greater than 50.

Table 27.   Setting the maxfan attribute in HDL Code
HDL Code
Verilog HDL
reg clk_gen /* synthesis syn_maxfan = 50 */;
(* maxfan = 50 *) reg clk_gen;
Table 28.   Setting the syn_maxfan attribute in HDL CodeThe Quartus® Prime software supports the syn_maxfan attribute for compatibility with other synthesis tools.
HDL Code
signal clk_gen : stdlogic;
attribute maxfan : signal ;
attribute maxfan of clk_gen : signal is 50;