Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

3.2.1.3. Initial Constructs and Memory System Tasks

The Intel® Quartus® Prime software infers power-up conditions from the Verilog HDL initial constructs. The Intel® Quartus® Prime software also creates power-up settings for variables, including RAM blocks. If the Intel® Quartus® Prime software encounters non-synthesizable constructs in an initial block, it generates an error.

To avoid such errors, enclose non-synthesizable constructs (such as those intended only for simulation) in translate_off and translate_on synthesis directives. Synthesis of initial constructs enables the power-up state of the synthesized design to match the power-up state of the original HDL code in simulation.

Note: Initial blocks do not infer power-up conditions in some third-party EDA synthesis tools. If you convert between synthesis tools, you must set your power-up conditions correctly.

Intel® Quartus® Prime synthesis supports the $readmemb and $readmemh system tasks to initialize memories.

Verilog HDL Code: Initializing RAM with the readmemb Command

reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end

When creating a text file to use for memory initialization, specify the address using the format @<location > on a new line, and then specify the memory word such as 110101 or abcde on the next line.

The following example shows a portion of a Memory Initialization File (.mif) for the RAM.

Text File Format: Initializing RAM with the readmemb Command

@0
00000000
@1
00000001
@2
00000010
…
@e
00001110
@f
00001111