Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

3.5.4. Resource Aware RAM, ROM, and Shift-Register Inference

The Intel® Quartus® Prime Integrated Synthesis considers resource usage when inferring RAM, ROM, and shift registers. During RAM, ROM, and shift register inferencing, synthesis looks at the number of memories available in the current device and does not infer more memory than is available to avoid a no-fit error. Synthesis tries to select the memories that are not inferred in a way that aims at the smallest increase in logic and registers.

Resource aware RAM, ROM and shift register inference is controlled by the Resource Aware Inference for Block RAM option. To disable this option for the entire project, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).

When you select the Auto setting, resource aware RAM, ROM, and shift register inference use the resource counts from the largest device.

For designs with multiple partitions, Intel® Quartus® Prime Integrated Synthesis considers one partition at a time. Therefore, for each partition, it assumes that all RAM blocks are available to that partition. If this causes a no-fit error, you can limit the number of RAM blocks available per partition with the Maximum Number of M512 Memory Blocks, Maximum Number of M4K/M9K/M20K/M10K Memory Blocks, Maximum Number of M-RAM/M144K Memory Blocks and Maximum Number of LABs settings in the Assignment Editor. The balancer also uses these options.

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