Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Virtual Pin Timing Assignments in Design Partition Scripts

Design partition scripts use INPUT_MAX_DELAY and OUTPUT_MAX_DELAY assignments to specify inter-partition delays associated with input and output pins, which would not otherwise be visible to the project. These assignments require that the software specify the clock domain for the assignment and set this clock domain to ” * ”.

This clock domain assignment means that there may be some paths constrained and reported by the timing analysis engine that are not required.

To restrict which clock domains are included in these assignments, edit the generated scripts or change the assignments in your lower‑level Intel® Quartus® Prime project. In addition, because there is no known clock associated with the delay assignments, the software assumes the worst‑case skew, which makes the paths seem more timing critical than they are in the top-level design. To make the paths appear less timing‑critical, lower the delay values from the scripts. If required, enter negative numbers for input and output delay values.