Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.5.2. Shift Registers

Use the Auto Shift Register Replacement logic option to control shift register inference. This option has three settings: Off, Auto and Always. Auto is the default setting in which Quartus® Prime Integrated Synthesis decides which shift registers to replace or leave in registers. Placing shift registers in memory saves logic area, but can have a negative effect on fmax. Quartus® Prime Integrated Synthesis uses the optimization technique setting, logic and RAM utilization of your design, and timing information from Timing-Driven Synthesis to determine which shift registers are located in memory and which are located in registers. To disable inference, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). You can also disable the option for a specific block with the Assignment Editor. Even if you set the logic option to On or Auto, the software might not infer small shift registers because small shift registers do not benefit from implementation in dedicated memory. However, you can use the Allow Any Shift Register Size for Recognition logic option to instruct synthesis to infer a shift register even when its size is too small.

You can use the Allow Shift Register Merging across Hierarchies option to prevent the Compiler from merging shift registers in different hierarchies into one larger shift register. The option has three settings: On, Off, and Auto. The Auto setting is the default setting, and the Compiler decides whether or not to merge shift registers across hierarchies. When you turn on this option, the Compiler allows all shift registers to merge across hierarchies, and when you turn off this option, the Compiler does not allow any shift registers to merge across hierarchies. You can set this option globally or on entities or individual nodes.

Note: The registers that the software maps to the RAM-based Shift Register IP core and places in RAM are not available in the Simulator because their node names do not exist after synthesis.

The Compiler turns off the Auto Shift Register Replacement logic option when you select a formal verification tool on the EDA Tool Settings page. If you do not select a formal verification tool, the Compiler issues a warning and the compilation report lists shift registers that the logic option might infer. To enable an IP core for the shift register in the formal verification flow, you can either instantiate a shift register explicitly with the IP catalog or make the shift register into a black box in a separate entity or module.