- 126.96.36.199. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 188.8.131.52. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.5.16. Use I/O Flipflops
The useioff attribute directs the Intel® Quartus® Prime software to implement input, output, and output enable flipflops (or registers) in I/O cells that have fast, direct connections to an I/O pin, when possible. To improve I/O performance by minimizing setup, clock-to-output, and clock-to-output enable times, you can apply the useioff synthesis attribute. The Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options support this synthesis attribute. You can also set this synthesis attribute in the Assignment Editor.
The useioff synthesis attribute takes a boolean value. You can apply the value only to the port declarations of a top-level Verilog HDL module or VHDL entity (it is ignored if applied elsewhere). Setting the value to 1 (Verilog HDL) or TRUE (VHDL) instructs the Intel® Quartus® Prime software to pack registers into I/O cells. Setting the value to 0 (Verilog HDL) or FALSE (VHDL) prevents register packing into I/O cells.
In Table 55 and Table 56, the useioff synthesis attribute directs the Intel® Quartus® Prime software to implement the a_reg, b_reg, and o_reg registers in the I/O cells corresponding to the a, b, and o ports, respectively.
Table 56 and Table 57 show that the Verilog-2001 syntax also accepts the type of statements instead of the comment form in Table 55.
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