Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

3.5.16. Use I/O Flipflops

The useioff attribute directs the Intel® Quartus® Prime software to implement input, output, and output enable flipflops (or registers) in I/O cells that have fast, direct connections to an I/O pin, when possible. To improve I/O performance by minimizing setup, clock-to-output, and clock-to-output enable times, you can apply the useioff synthesis attribute. The Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options support this synthesis attribute. You can also set this synthesis attribute in the Assignment Editor.

The useioff synthesis attribute takes a boolean value. You can apply the value only to the port declarations of a top-level Verilog HDL module or VHDL entity (it is ignored if applied elsewhere). Setting the value to 1 (Verilog HDL) or TRUE (VHDL) instructs the Intel® Quartus® Prime software to pack registers into I/O cells. Setting the value to 0 (Verilog HDL) or FALSE (VHDL) prevents register packing into I/O cells.

In Table 55 and Table 56, the useioff synthesis attribute directs the Intel® Quartus® Prime software to implement the a_reg, b_reg, and o_reg registers in the I/O cells corresponding to the a, b, and o ports, respectively.

Table 55.  Verilog HDL Code: The useioff Attribute
HDL Code
Verilog HDL
module top_level(clk, a, b, o);
       input clk;
       input [1:0] a, b /* synthesis useioff = 1 */;
       output [2:0] o /* synthesis useioff = 1 */;
       reg [1:0] a_reg, b_reg;
       reg [2:0] o_reg;
       always @ (posedge clk) 
       begin
           a_reg <= a;
           b_reg <= b;
           o_reg <= a_reg + b_reg; 
       end
       assign o = o_reg;
endmodule

Table 56 and Table 57 show that the Verilog-2001 syntax also accepts the type of statements instead of the comment form in Table 55.

Table 56.  Verilog-2001 Code: the useioff Attribute
HDL Code
Verilog-2001
(* useioff = 1 *)   input [1:0] a, b;
(* useioff = 1 *)   output [2:0] o;
Table 57.  VHDL Code: the useioff Attribute
HDL Code
VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity useioff_example is
   port (
      clk  : in  std_logic;
      a, b : in  unsigned(1 downto 0);
      o    : out unsigned(1 downto 0));
   attribute useioff : boolean;
   attribute useioff of a : signal is true;
   attribute useioff of b : signal is true;
   attribute useioff of o : signal is true;
end useioff_example;
architecture rtl of useioff_example is
   signal o_reg, a_reg, b_reg : unsigned(1 downto 0);
begin 
   process(clk)
   begin
      if (clk = '1' AND clk'event) then
          a_reg <= a;
          b_reg <= b;
          o_reg <= a_reg + b_reg;
      end if;   
   end process;
o <= o_reg;
end rtl;