- 184.108.40.206. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 220.127.116.11. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.1. Design Flow
The Intel® Quartus® Prime Analysis & Synthesis stage of the compilation flow runs Integrated Synthesis, which fully supports Verilog HDL, VHDL, and Altera-specific languages, and major features of the SystemVerilog language.
In the synthesis stage of the compilation flow, the Intel® Quartus® Prime software performs logic synthesis to optimize design logic and performs technology mapping to implement the design logic in device resources such as logic elements (LEs) or adaptive logic modules (ALMs), and other dedicated logic blocks. The synthesis stage generates a single project database that integrates all your design files in a project (including any netlists from third-party synthesis tools).
You can use Analysis & Synthesis to perform the following compilation processes:
|Analyze Current File||Parses your current design source file to check for syntax errors. This command does not report many semantic errors that require further design synthesis. To perform this analysis, on the Processing menu, click Analyze Current File.|
|Analysis & Elaboration||Checks your design for syntax and semantic errors and performs elaboration to identify your design hierarchy. To perform Analysis & Elaboration, on the Processing menu, point to Start, and then click Start Analysis & Elaboration.|
|Hierarchy Elaboration||Parses HDL designs and generates a skeleton of hierarchies. Hierarchy Elaboration is similar to the Analysis & Elaboration flow, but without any elaborated logic, thus making it much faster to generate.|
|Analysis & Synthesis||Performs complete Analysis & Synthesis on a design, including technology mapping. To perform Analysis & Synthesis, on the Processing menu, point to Start, and then click Start Analysis & Synthesis.|
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