Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.20. Disabling Synthesis Netlist Optimizations with dont_retime Attribute

This attribute disables synthesis retiming optimizations on the register you specify. When applied to a design entity, it applies to all registers in the entity.

You can turn off retiming optimizations with this option and prevent node name changes, so that the Compiler can correctly use your timing constraints for the register.

You can set the Netlist Optimizations logic option to Never Allow in the Quartus® Prime software to disable retiming along with other synthesis netlist optimizations, or you can set the dont_retime attribute in your HDL code, as shown in the following table. In the following table, the code prevents my_reg register from being retimed.

Table 25.  Setting the dont_retime Attribute in HDL Code
HDL Code
Verilog HDL
reg my_reg /* synthesis dont_retime */;
Verilog-2001 and SystemVerilo
(* dont_retime *) reg my_reg;
signal my_reg : std_logic;
attribute dont_retime : boolean;
attribute dont_retime of my_reg : signal is true;
Note: For compatibility with third-party synthesis tools, Quartus® Prime Integrated Synthesis also supports the attribute syn_allow_retiming. To disable retiming, set syn_allow_retiming to 0 (Verilog HDL) or false (VHDL). This attribute does not have any effect when you set the attribute to 1 or true.