- 22.214.171.124. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 126.96.36.199. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.20. Disabling Synthesis Netlist Optimizations with dont_retime Attribute
This attribute disables synthesis retiming optimizations on the register you specify. When applied to a design entity, it applies to all registers in the entity.
You can turn off retiming optimizations with this option and prevent node name changes, so that the Compiler can correctly use your timing constraints for the register.
You can set the Netlist Optimizations logic option to Never Allow in the Intel® Quartus® Prime software to disable retiming along with other synthesis netlist optimizations, or you can set the dont_retime attribute in your HDL code, as shown in the following table. In the following table, the code prevents my_reg register from being retimed.
reg my_reg /* synthesis dont_retime */;
|Verilog-2001 and SystemVerilo||
(* dont_retime *) reg my_reg;
signal my_reg : std_logic; attribute dont_retime : boolean; attribute dont_retime of my_reg : signal is true;
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