Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

3.3.2. Parallel Synthesis

The Parallel Synthesis logic option reduces compilation time for synthesis. The option enables the Intel® Quartus® Prime software to use multiple processors to synthesize multiple partitions in parallel.

This option is available when you perform the following tasks:

  • Specify the maximum number of processors allowed under Parallel Compilation options in the Compilation Process Settings page of the Settings dialog box.
  • Enable the incremental compilation feature.
  • Use two or more partitions in your design.
  • Turn on the Parallel Synthesis option.

By default, the Intel® Quartus® Prime software enables the Parallel Synthesis option. To disable parallel synthesis, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) > Parallel Synthesis.

You can also set the Parallel Synthesis option with the following Tcl command:

set_global_assignment -name parallel_synthesis off

If you use the command line, you can differentiate among the interleaved messages by turning on the Show partition that generated the message option in the Messages page. This option shows the partition ID in parenthesis for each message.

You can view all the interleaved messages from different partitions in the Messages window. The Partition column in the Messages window displays the partition ID of the partition referred to in the message. After compilation, you can sort the messages by partition.

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