Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

3.10. Document Revision History

Table 72.  Document Revision History
Date Version Changes
2018.09.24 18.1.0
  • Added Factors Affecting Compilation Results topic.
  • Removed references to VHDL-2008 synthesis support. This support was listed in error and VHDL-2008 is only supported in Intel® Quartus® Prime Pro Edition
2016.05.03 16.0.0 Corrected description of Fitter Intial Placement Seed option.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0
  • Removed support for early timing estimate feature.
  • Removed the note on the assignment of the RAM style attributes as it is no longer relevant.
2014.12.15 14.1.0 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
2014.06.30 14.0.0 Template update.
November 2013 13.1.0
  • Added a note regarding ROM inference using the ram_init_file in “RAM Initialization File—for Inferred Memory” on page 16–61.
May 2013 13.0.0
  • Added “Verilog HDL Configuration” on page 16–6.
  • Added “RAM Style Attribute—For Shift Registers Inference” on page 16–57.
  • Added “Upgrade IP Components Dialog Box” on page 16–75.
June 2012 12.0.0
  • Updated “Design Flow” on page 16–2.
November 2011 11.1.0
  • Updated “Language Support” on page 16–5, “Incremental Compilation” on page 16–22, “ Intel® Quartus® Prime Synthesis Options” on page 16–24.
May 2011 11.0.0
  • Updated “Specifying Pin Locations with chip_pin” on page 14–65, and “Shift Registers” on page 14–48.
  • Added a link to Intel® Quartus® Prime Help in “SystemVerilog Support” on page 14–5.
  • Added Example 14–106 and Example 14–107 on page 14–67.
December 2010 10.1.0
  • Updated “Verilog HDL Support” on page 13–4 to include Verilog-2001 support.
  • Updated “VHDL-2008 Support” on page 13–9 to include the condition operator (explicit and implicit) support.
  • Rewrote “Limiting Resource Usage in Partitions” on page 13–32.
  • Added “Creating LogicLock Regions” on page 13–32 and “Using Assignments to Limit the Number of RAM and DSP Blocks” on page 13–33.
  • Updated “Turning Off the Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute” on page 13–55.
  • Updated “Auto Gated Clock Conversion” on page 13–28.
  • Added links to Intel® Quartus® Prime Help.
July 2010 10.0.0
  • Removed Referenced Documents section.
  • Added “Synthesis Seed” on page 9–36 section.
  • Updated the following sections:

    “SystemVerilog Support” on page 9–5

    “VHDL-2008 Support” on page 9–10

    “Using Parameters/Generics” on page 9–16

    “Parallel Synthesis” on page 9–21

    “Limiting Resource Usage in Partitions” on page 9–32

    “Synthesis Effort” on page 9–35

    “Synthesis Attributes” on page 9–25

    “Synthesis Directives” on page 9–27

    “Auto Gated Clock Conversion” on page 9–29

    “State Machine Processing” on page 9–36

    “Multiply-Accumulators and Multiply-Adders” on page 9–50

    “Resource Aware RAM, ROM, and Shift-Register Inference” on page 9–52

    “RAM Style and ROM Style—for Inferred Memory” on page 9–53

    “Turning Off the Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute” on page 9–55

    “Using altera_attribute to Set Intel® Quartus® Prime Logic Options” on page 9–68

    “Adding an HDL File to a Project and Setting the HDL Version” on page 9–83

    “Creating Design Partitions for Incremental Compilation” on page 9–85

    “Inferring Multiplier, DSP, and Memory Functions from HDL Code” on page 9–50

  • Updated Table 9–9 on page 9–86.
December 2009 9.1.1
  • Added information clarifying inheritance of Synthesis settings by lower-level entities, including Altera and third-party IP
  • Updated “Keep Combinational Node/Implement as Output of Logic Cell” on page 9–46
November 2009 9.1.0
  • Updated the following sections:

    “Initial Constructs and Memory System Tasks” on page 9–7

    “VHDL Support” on page 9–9

    “Parallel Synthesis” on page 9–21

    “Synthesis Directives” on page 9–27

    “Timing-Driven Synthesis” on page 9–31

    “Safe State Machines” on page 9–40

    “RAM Style and ROM Style—for Inferred Memory” on page 9–53

    “Translate Off and On / Synthesis Off and On” on page 9–62

    “Read Comments as HDL” on page 9–63

    “Adding an HDL File to a Project and Setting the HDL Version” on page 9–81

  • Removed “Remove Redundant Logic Cells” section
  • Added “Resource Aware RAM, ROM, and Shift-Register Inference” section
  • Updated Table 9–9 on page 9–83
March 2009 9.0.0
  • Updated Table 9–9.
  • Updated the following sections:

    “Partitions for Preserving Hierarchical Boundaries” on page 9–20

    “Analysis & Synthesis Settings Page of the Settings Dialog Box” on page 9–24

    “Timing-Driven Synthesis” on page 9–30

    “Turning Off Add Pass-Through Logic to Inferred RAMs/ no_rw_check Attribute Setting” on page 9–54

  • Added “Parallel Synthesis” on page 9–21
  • Chapter 9 was previously Chapter 8 in software version 8.1