Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.11. State Machine Processing

The State Machine Processing logic option specifies the processing style to synthesize a state machine.

The default state machine encoding, Auto, uses one-hot encoding for FPGA devices and minimal-bits encoding for CPLDs. These settings achieve the best results on average, but another encoding style might be more appropriate for your design, so this option allows you to control the state machine encoding.

For one-hot encoding, the Quartus® Prime software does not guarantee that each state has one bit set to one and all other bits set to zero. Quartus® Prime Integrated Synthesis creates one-hot register encoding with standard one-hot encoding and then inverts the first bit. This results in an initial state with all zero values, and the remaining states have two 1 values. Quartus® Prime Integrated Synthesis encodes the initial state with all zeros for the state machine power-up because all device registers power up to a low value. This encoding has the same properties as true one-hot encoding: the software recognizes each state by the value of one bit. For example, in a one-hot-encoded state machine with five states, including an initial or reset state, the software uses the following register encoding:

State 0    0 0 0 0 0  
State 1    0 0 0 1 1  
State 2    0 0 1 0 1  
State 3    0 1 0 0 1  
State 4    1 0 0 0 1

If you set the State Machine Processing logic option to User-Encoded in a Verilog HDL design, the software starts with the original design values for the state constants. For example, a Verilog HDL design can contain the following declaration:

parameter S0 = 4'b1010, S1 = 4'b0101, ...

If the software infers the states S0, S1,... the software uses the encoding 4'b1010, 4'b0101,... . If necessary, the software inverts bits in a user-encoded state machine to ensure that all bits of the reset state of the state machine are zero.

Note: You can view the state machine encoding from the Compilation Report under the State Machines of the Analysis & Synthesis Report. The State Machine Viewer displays only a graphical representation of the state machines as interpreted from your design.

To assign your own state encoding with the User-Encoded setting of the State Machine Processing option in a VHDL design, you must apply specific binary encoding to the elements of an enumerated type because enumeration literals have no numeric values in VHDL. Use the syn_encoding synthesis attribute to apply your encoding values.