Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.16. Preserve Registers

This attribute and logic option directs the Compiler not to minimize or remove a specified register during synthesis optimizations or register netlist optimizations. Optimizations can eliminate redundant registers and registers with constant drivers; this option prevents the software from reducing a register to a constant or merging with a duplicate register. This option can preserve a register so you can observe the register during simulation or with the Signal Tap. Additionally, this option can preserve registers if you create a preliminary version of your design in which you have not specified the secondary signals. You can also use the attribute to preserve a duplicate of an I/O register so that you can place one copy of the I/O register in an I/O cell and the second in the core.

Note: This option cannot preserve registers that have no fan-out.

The Preserve Registers logic option prevents the software from inferring a register as a state machine.

You can set the Preserve Registers logic option in the Quartus® Prime software, or you can set the preserve attribute in your HDL code. In these examples, the Quartus® Prime software preserves the my_reg register.

Table 19.  Setting the syn_preserve attribute in HDL Code
HDL Code5
Verilog HDL
reg my_reg /* synthesis syn_preserve = 1 */;
(* syn_preserve = 1 *) reg my_reg;
Table 20.  Setting the preserve attribute in HDL Code In addition to preserve, the Quartus® Prime software supports the syn_preserve attribute name for compatibility with other synthesis tools.
HDL Code
signal my_reg : stdlogic;
attribute preserve : boolean;
attribute preserve of my_reg : signal is true;
5 The = 1 after the preserve are optional, because the assignment uses a default value of 1 when you specify the assignment.