- 22.214.171.124. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 126.96.36.199. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.19. Keep Combinational Node/Implement as Output of Logic Cell
This synthesis attribute and corresponding logic option direct the Compiler to keep a wire or combinational node through logic synthesis minimizations and netlist optimizations. A wire that has a keep attribute or a node that has the Implement as Output of Logic Cell logic option applied becomes the output of a logic cell in the final synthesis netlist, and the name of the logic cell remains the same as the name of the wire or node. You can use this directive to make combinational nodes visible to the Signal Tap.
You can use the Ignore LCELL Buffers logic option to direct Analysis & Synthesis to ignore logic cell buffers that the Implement as Output of Logic Cell logic option or the LCELL primitive created. If you apply this logic option to an entity, it affects all lower-level entities in the hierarchy path.
You can turn off the Ignore LCELL Buffers logic option for a specific entity to override any assignments inherited from higher-level entities in the hierarchy path if logic cell buffers created by the Implement as Output of Logic Cell logic option or the LCELL primitive are required for correct behavior.
You can set the Implement as Output of Logic Cell logic option in the Intel® Quartus® Prime software, or you can set the keep attribute in your HDL code, as shown in these tables. In these tables, the Compiler maintains the node name my_wire.
wire my_wire /* synthesis keep = 1 */;
(* keep = 1 *) wire my_wire;
signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true;
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