ID 683283
Date 9/24/2018
Public

3.4.19. Keep Combinational Node/Implement as Output of Logic Cell

This synthesis attribute and corresponding logic option direct the Compiler to keep a wire or combinational node through logic synthesis minimizations and netlist optimizations. A wire that has a keep attribute or a node that has the Implement as Output of Logic Cell logic option applied becomes the output of a logic cell in the final synthesis netlist, and the name of the logic cell remains the same as the name of the wire or node. You can use this directive to make combinational nodes visible to the Signal Tap.

Note: The option cannot keep nodes that have no fan-out. You cannot maintain node names for wires with tri-state drivers, or if the signal feeds a top-level pin of the same name (the software changes the node name to a name such as <net name>~buf0).

You can use the Ignore LCELL Buffers logic option to direct Analysis & Synthesis to ignore logic cell buffers that the Implement as Output of Logic Cell logic option or the LCELL primitive created. If you apply this logic option to an entity, it affects all lower-level entities in the hierarchy path.

Note: To avoid unintended design optimizations, ensure that any entity instantiated with Altera or third-party IP that relies on logic cell buffers for correct behavior does not inherit the Ignore LCELL Buffers logic option. For example, if an IP core uses logic cell buffers to manage high fan-out signals and inherits the Ignore LCELL Buffers logic option, the target device may no longer function properly.

You can turn off the Ignore LCELL Buffers logic option for a specific entity to override any assignments inherited from higher-level entities in the hierarchy path if logic cell buffers created by the Implement as Output of Logic Cell logic option or the LCELL primitive are required for correct behavior.

You can set the Implement as Output of Logic Cell logic option in the Intel® Quartus® Prime software, or you can set the keep attribute in your HDL code, as shown in these tables. In these tables, the Compiler maintains the node name my_wire.

Table 23.   Setting the keep Attribute in HDL code
HDL Code
Verilog HD
wire my_wire /* synthesis keep = 1 */;
Verilog-2001
(* keep = 1 *) wire my_wire;
Table 24.  Setting the syn_keep Attribute in HDL CodeIn addition to keep, the Intel® Quartus® Prime software supports the syn_keep attribute name for compatibility with other synthesis tools.
HDL Code
VHDL
signal my_wire: bit;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;