Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.21. Disabling Synthesis Netlist Optimizations with dont_replicate Attribute

This attribute disables synthesis replication optimizations on the register you specify. When applied to a design entity, it applies to all registers in the entity.

You can turn off register replication (or duplication) optimizations with this option, so that the Compiler uses your timing constraints for the register.

You can set the Netlist Optimizations logic option to Never Allow in the Quartus® Prime software to disable replication along with other synthesis netlist optimizations, or you can set the dont_replicate attribute in your HDL code, as shown in these examples. In these examples, the code prevents the replication of the my_reg register.

Table 26.  Setting the dont_replicate attribute in HDL Code
HDL Code
Verilog HD
reg my_reg /* synthesis dont_replicate  */;
Verilog-2001 and SystemVerilog
(* dont_replicate *) reg my_reg;
signal my_reg : std_logic;
attribute dont_replicate : boolean;
attribute dont_replicate of my_reg : signal is true;
Note: For compatibility with third-party synthesis tools, Quartus® Prime Integrated Synthesis also supports the attribute syn_replicate. To disable replication, set syn_replicate to 0 (Verilog HDL) or false (VHDL). This attribute does not have any effect when you set the attribute to 1 or true.