- 184.108.40.206. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 220.127.116.11. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
18.104.22.168. Setting the HDL Message Level
The HDL Message Level specifies the types of messages that the Intel® Quartus® Prime software displays when it is analyzing and elaborating your design files.
|Level1||High-severity messages only||If you want to view only the HDL messages that identify likely problems with your design, select Level1. When you select Level1, the Intel® Quartus® Prime software issues a message only if there is an actual problem with your design.|
|Level2||High-severity and medium-severity messages||If you want to view additional HDL messages that identify possible problems with your design, select Level2. Level2 is the default setting.|
|Level3||All messages, including low-severity messages||If you want to view all HDL info and warning messages, select Level3. This level includes extra “LINT” messages that suggest changes to improve the style of your HDL code.|
You must address all issues reported at the Level1 setting. The default HDL message level is Level2.
To set the HDL Message Level in the Intel® Quartus® Prime software, follow these steps:
- Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)
- Set the necessary message level from the pull-down menu in the HDL Message Level list, and then click OK.
You can override this default setting in a source file with the message_level synthesis directive, which takes the values level1, level2, and level3, as shown in the following table.
Table 68. HDL Examples of message_level Directive HDL Code Verilog HDL
// altera message_level level1 or /* altera message_level level3 */
-- altera message_level level2
A message_level synthesis directive remains effective until the end of a file or until the next message_level directive. In VHDL, you can use the message_level synthesis directive to set the HDL Message Level for entities and architectures, but not for other design units. An HDL Message Level for an entity applies to its architectures, unless overridden by another message_level directive. In Verilog HDL, you can use the message_level directive to set the HDL Message Level for a module.
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