- 220.127.116.11. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 18.104.22.168. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
22.214.171.124. Assign Virtual Pins
You can create a virtual pin assignment in the Assignment Editor for partition I/Os that will become internal nodes in the top-level design. When you apply the Virtual Pin assignment to an input pin, the pin no longer appears as an FPGA pin, but is fixed to GND or VCC in the design. The assigned pin is not an open node. Leave the clock pins mapped to I/O pins to ensure proper routing.
You can specify locations for the virtual pins that correspond to the placement of other partitions, and also make timing assignments to the virtual pins to define a timing budget. Virtual pins are created automatically from the top-level design if you use design partition scripts. The scripts place the virtual pins to correspond with the placement of the other partitions in the top-level design.
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