Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

1.7.5.1.2. Synopsys Design Constraint Files for the Intel® Quartus® Prime Timing Analyzer

Timing assignments made for the Intel® Quartus® Prime Timing Analyzer in a Synopsys Design Constraint File (.sdc) in the lower-level partition project are not added to the top-level design. Ensure that the top-level design includes all of the timing requirements for the entire project.