- 22.214.171.124. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 126.96.36.199. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.4. Enabling Timing-Driven Synthesis
Timing-driven synthesis preserves timing constraints, and does not perform optimizations that conflict with timing constraints. Timing-driven synthesis may increase the number of required device resources. Specifically, the number of adaptive look-up tables (ALUTs) and registers may increase. The overall area can increase or decrease. Runtime and peak memory use increases slightly.
Timing-Driven Synthesis prevents registers with incompatible timing constraints from merging for any Optimization Technique setting. If your design contains multiple partitions, you can select Timing-Driven Synthesis options for each partition. If you use a .qxp as a source file, or if your design uses partitions developed in separate Intel® Quartus® Prime projects, the software cannot properly compute timing of paths that cross the partition boundaries.
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