Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Synthesis Attributes in VHDL

VHDL attributes declare and apply the attribute type to the object you specify.

Synthesis Attributes in VHDL

The following shows the synthesis attributes example in VHDL:

attribute <attribute> : <attribute type> ;
attribute <attribute> of <object> : <object type> is <value>;


The Intel® Quartus® Prime software defines and applies each attribute separately to a given node. For VHDL designs, the software declares all supported synthesis attributes in the altera_syn_attributes package in the Altera library. You can call this library from your VHDL code to declare the synthesis attributes:

LIBRARY altera;
USE altera.altera_syn_attributes.all;

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