Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Additional Planning Needed

Teams with a bottom-up design approach often want to optimize placement and routing of design partitions independently and may want to create separate Intel® Quartus® Prime projects for each partition. However, optimizing design partitions in separate Intel® Quartus® Prime projects, and then later integrating the results into a top-level design, can have the following potential drawbacks that require careful planning:
  • Achieving timing closure for the full design may be more difficult if you compile partitions independently without information about other partitions in the design. This problem may be avoided by careful timing budgeting and special design rules, such as always registering the ports at the module boundaries.
  • Resource budgeting and allocation may be required to avoid resource conflicts and overuse. Creating a floorplan with LogicLock regions is recommended when design partitions are developed independently in separate Intel® Quartus® Prime projects.
  • Maintaining consistency of assignments and timing constraints can be more difficult if there are separate Intel® Quartus® Prime projects. The project lead must ensure that the top-level design and the separate projects are consistent in their assignments.