ID 683283
Date 9/24/2018
Public

## 3.9.1. Adding an HDL File to a Project and Setting the HDL Version

To add an HDL or schematic entry design file to your project, use the Tcl assignments shown in this example:

set_global_assignment –name VERILOG_FILE <file name>.<v|sv> set_global_assignment –name SYSTEMVERILOG_FILE <file name>.sv set_global_assignment –name VHDL_FILE <file name>.<vhd|vhdl> set_global_assignment -name AHDL_FILE <file name>.tdf set_global_assignment -name BDF_FILE <file name>.bdf
Note: You can use any file extension for design files, as long as you specify the correct language when adding the design file. For example, you can use .h for Verilog HDL header files.

To specify the Verilog HDL or VHDL version, use the option shown in this example, at the end of the VERILOG_FILE or VHDL_FILE command:

-	HDL_VERSION <language version>

The variable <language version> takes one of the following values:

• VERILOG_1995
• VERILOG_2001
• SYSTEMVERILOG_2005
• VHDL_1987
• VHDL_1993
• VHDL_2008

For example, to add a Verilog HDL file called my_file.v written in Verilog-1995, use the command shown in this example:

set_global_assignment –name VERILOG_FILE my_file.v –HDL_VERSION \ VERILOG_1995

In this example, the syn_encoding attribute associates a binary encoding with the states in the enumerated type count_state. In this example, the states are encoded with the following values: zero = "11", one = "01", two = "10", three = "00".

ARCHITECTURE rtl OF my_fsm IS
TYPE count_state is (zero, one, two, three);
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF count_state : TYPE IS "11 01 10 00";
SIGNAL present_state, next_state : count_state;
BEGIN

You can also use the syn_encoding attribute in Verilog HDL to direct the synthesis tool to use the encoding from your HDL code, instead of using the State Machine Processing option.

The syn_encoding value "user" instructs the Intel® Quartus® Prime software to encode each state with its corresponding value from the Verilog HDL source code. By changing the values of your state constants, you can change the encoding of your state machine.

In Verilog-2001 and SystemVerilog Code: Specifying User-Encoded States with the syn_encoding Attribute, the states are encoded as follows:

init = "00" last = "11" next = "01" later = "10"

### Verilog-2001 and SystemVerilog Code: Specifying User-Encoded States with the syn_encoding Attribute

(* syn_encoding = "user" *) reg [1:0] state;
parameter init = 0, last = 3, next = 1, later = 2;
always @ (state) begin
case (state)
init:
out = 2'b01;
next:
out = 2'b10;
later:
out = 2'b11;
last:
out = 2'b00;
endcase
end

Without the syn_encoding attribute, the Intel® Quartus® Prime software encodes the state machine based on the current value of the State Machine Processing logic option.

If you also specify a safe state machine (as described in Safe State Machine), separate the encoding style value in the quotation marks from the safe value with a comma, as follows: “safe, one-hot” or “safe, gray”.