Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

2.11.1. Create a Floorplan for Major Design Blocks

Use this incremental compilation flow for designs when you want to assign a floorplan location for each major block in your design. A full floorplan ensures that partitions do not interact as they are changed and recompiled— each partition has its own area of the device floorplan.

To create a floorplan for major design blocks, follow this general methodology:

  1. In the Design Partitions window, ensure that all partitions have their netlist type set to Source File or Post-Synthesis. If the netlist type is set to Post-Fit, floorplan location assignments are not used when recompiling the design.
  2. Create a LogicLock region for each partition (including the top-level entity, which is set as a partition by default).
  3. Run a full compilation of your design to view the initial Fitter-chosen placement of the LogicLock regions as a guideline.
  4. In the Chip Planner, view the placement results of each partition and LogicLock region on the device.
  5. If required, modify the size and location of the LogicLock regions in the Chip Planner. For example, enlarge the regions to fill up the device and allow for future logic changes.You can also, if needed, create a new LogicLock region by drawing a box around an area on the floorplan.
  6. Run the Compiler with the Start Compilation command to determine the timing performance of your design with the modified or new LogicLock regions.
  7. Repeat steps 5 and 6 until you are satisfied with the quality of results for your design floorplan. Once you are satisfied with your results, run a full compilation of your design.