- 126.96.36.199. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 188.8.131.52. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
1.4.4. Debugging Incrementally With the Signal Tap Logic Analyzer
Use this flow to reduce compilation times when you add the logic analyzer to debug your design, or when you want to modify the configuration of the Signal Tap File without modifying your design logic or its placement.
It is not necessary to create design partitions in order to use the Signal Tap incremental compilation feature. The Signal Tap Logic Analyzer acts as its own separate design partition.
Perform the following steps to use the Signal Tap Logic Analyzer in an incremental compilation flow:
- Open the Design Partitions window.
- Set the netlist type to Post-fit for all partitions to preserve their placement.
- The netlist type for the top-level partition defaults to Source File, so be sure to change this “Top” partition in addition to any design partitions that you have created.
- If you have not already compiled the design with the current set of partitions, perform a full compilation. If the design has already been compiled with the current set of partitions, the design is ready to add the Signal Tap Logic Analyzer.
- Set up your SignalTap II File using the post-fitting filter in the Node Finder to add signals for logic analysis. This allows the Fitter to add the SignalTap II logic to the post-fit netlist without modifying the design results.
To add signals from the pre-synthesis netlist, set the partition’s netlist type to Source File and use the presynthesis filter in the Node Finder. This allows the software to resynthesize the partition and to tap directly to the pre‑synthesis node names that you choose. In this case, the partition is resynthesized and refit, so the placement is typically different from previous fitting results.
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