- 126.96.36.199. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 188.8.131.52. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
184.108.40.206. Allocate Logic Resources
You can constrain logic utilization for the IP core using design floorplan location assignments. The design should specify I/O pin locations with pin assignments.
You can also specify limits for Intel® Quartus® Prime synthesis to allocate and balance resources. This procedure can also help if device resources are overused in the individual partitions during synthesis.
In the standard synthesis flow, the Intel® Quartus® Prime software can perform automated resource balancing for DSP blocks or RAM blocks and convert some of the logic into regular logic cells to prevent overuse.
You can use the Intel® Quartus® Prime synthesis options to control inference of IP cores that use the DSP, or RAM blocks. You can also use the IP Catalog and Parameter Editor to customize your RAM or DSP IP cores to use regular logic instead of the dedicated hardware blocks.
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