Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.5.3. RAM and ROM

Use the Auto RAM Replacement and Auto ROM Replacement logic options to control RAM and ROM inference, respectively. To disable the inference, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).

Note: Although the software implements inferred shift registers in RAM blocks, you cannot turn off the Auto RAM Replacement option to disable shift register replacement. Use the Auto Shift Register Replacement option.

The software might not infer very small RAM or ROM blocks because you can implement very small memory blocks with the registers in the logic. However, you can use the Allow Any RAM Size for Recognition and Allow Any ROM Size for Recognition logic options to instruct synthesis to infer a memory block even when its size is too small.

Note: The software turns off the Auto ROM Replacement logic option when you select a formal verification tool in the EDA Tool Settings page. If you do not select a formal verification tool, the software issues a warning and a report panel provides a list of ROMs that the logic option might infer. To enable an IP core for the shift register in the formal verification flow, you can either instantiate a ROM explicitly using the IP Catalog or create a black box for the ROM in a separate entity or in a separate module.

Although formal verification tools do not support inferred RAM blocks, due to the importance of inferring RAM in many designs, the software turns on the Auto RAM Replacement logic option when you select a formal verification tool in the EDA Tool Settings page. The software automatically performs black box instance for any module or entity that contains an inferred RAM block. The software issues a warning and lists the black box created in the compilation report. This black box allows formal verification tools to proceed; however, the formal verification tool cannot verify the entire module or entire entity that contains the RAM. Altera recommends that you explicitly instantiate RAM blocks in separate modules or in separate entities so that the formal verification tool can verify as much logic as possible.