Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

1.12. Document Revision History

Table 6.  Document Revision History

Date

Version

Changes

2016.05.03 16.0.0 Stated limitations about deprecated physical synthesis options.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0 Removed Early Timing Estimate feature support.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
  • Updated DSE II content.

2014.08.18

14.0a10.0

Added restriction about smart compilation in Arria 10 devices.

June 2014

14.0.0

  • Dita conversion.
  • Replaced MegaWizard Plug-In Manager content with IP Catalog and Parameter Editor content.
  • Revised functional safety section. Added export and import sections.

November 2013

13.1.0

Removed HardCopy device information. Revised information about Rapid Recompile. Added information about functional safety. Added information about flattening sub-partition hierarchies.

November 2012

12.1.0

Added Turning On Supported Cross-boundary Optimizations.

June 2012

12.0.0

Removed survey link.

November 2011

11.0.1

Template update.

May 2011

11.0.0

  • Updated “Tcl Scripting and Command-Line Examples”.

December 2010

10.1.0

  • Changed to new document template.
  • Reorganized Tcl scripting section. Added description for new feature: Ignore partitions assignments during compilation option.
  • Reorganized “Incremental Compilation Summary” section.

July 2010

10.0.0

  • Removed the explanation of the “bottom-up design flow” where designers work completely independently, and replaced with Altera’s recommendations for team-based environments where partitions are developed in the same top-level project framework, plus an explanation of the bottom-up process for including independent partitions from third-party IP designers.
  • Expanded the Merge command explanation to explain how it now accommodates cross-partition boundary optimizations.
  • Restructured Altera recommendations for when to use a floorplan.
  • Added “Viewing the Contents of a Intel® Quartus® Prime Exported Partition File (.qxp)” section.
  • Reorganized chapter to make design flow scenarios more visible; integrated into various sections rather than at the end of the chapter.

October 2009

9.1.0

  • Redefined the bottom-up design flow as team-based and reorganized previous design flow examples to include steps on how to pass top-level design information to lower-level designers.
  • Moved SDC Constraints from Lower-Level Partitions section to the Best Practices for Incremental Compilation Partitions and Floorplan Assignments chapter in volume 1 of the Intel® Quartus® Prime Handbook.
  • Reorganized the “Conclusion” section.
  • Removed HardCopy APEX and HardCopy Stratix Devices section.

March 2009

9.0.0

  • Split up netlist types table
  • Moved “Team-Based Incremental Compilation Design Flow” into the “Including or Integrating partitions into the Top-Level Design” section.
  • Added new section “Including or Integrating Partitions into the Top-Level Design”.
  • Removed “Exporting a Lower-Level Partition that Uses a JTAG Feature” restriction
  • Other edits throughout chapter

November 2008

8.1.0

  • Added new section “Importing SDC Constraints from Lower-Level Partitions” on page 2–44
  • Removed the Incremental Synthesis Only option
  • Removed section “OpenCore Plus Feature for MegaCore Functions in Bottom-Up Flows”
  • Removed section “Compilation Time with Physical Synthesis Optimizations”
  • Added information about using a .qxp as a source design file without importing
  • Reorganized several sections
  • Updated Figure 2–10