Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

1.10.6. Signal Tap Logic Analyzer in Exported Partitions

You can use the Signal Tap Embedded Logic Analyzer in any project that you can compile and program into an Altera device.

When incremental compilation is turned on, debugging logic is added to your design incrementally and you can tap post-fitting nodes and modify triggers and configuration without recompiling the full design. Use the appropriate filter in the Node Finder to find your node names. Use Signal Tap: post-fitting if the netlist type is Post-Fit to incrementally tap node names in the post-fit netlist database. Use Signal Tap: pre-synthesis if the netlist type is Source File to make connections to the source file (pre-synthesis) node names when you synthesize the partition from the source code.

If incremental compilation is turned off, the debugging logic is added to the design during Analysis and Elaboration, and you cannot tap post-fitting nodes or modify debug settings without fully compiling the design.

For design partitions that are being developed independently in separate Quartus® Prime projects and contain the logic analyzer, when you export the partition, the Quartus® Prime software automatically removes the Signal Tap logic analyzer and related SLD_HUB logic. You can tap any nodes in a Quartus® Prime project, including nodes within .qxp partitions. Therefore, you can use the logic analyzer within the full top-level design to tap signals from the .qxp partition.

You can also instantiate the Signal Tap IP core directly in your lower‑level design (instead of using an .stp file) and export the entire design to the top level to include the logic analyzer in the top-level design.