The chip_pin attribute allows you to assign pin locations in your HDL source. You can use the attribute only on the ports of the top-level entity or module in your design. You can assign pins only to single-bit or one-dimensional bus ports in your design.
For single-bit ports, the value of the chip_pin attribute is the name of the pin on the target device, as specified by the pin table of the device.
Note: In addition to the chip_pin attribute, the Intel® Quartus® Prime software supports the altera_chip_pin_lc attribute name for compatibility with other synthesis tools. When using this attribute in other synthesis tools, some older device families require an “@” symbol in front of each pin assignment. In the Intel® Quartus® Prime software, the “@” is optional.
Table 58. Applying Chip Pin to a Single PinThese examples in this table show different ways of assigning my_pin1 to Pin C1 and my_pin2 to Pin 4 on a different target device.
HDL |
Code |
Verilog-1995 |
input my_pin1 /* synthesis chip_pin = "C1" */;
input my_pin2 /* synthesis altera_chip_pin_lc = "@4" */; |
Verilog-2001 |
(* chip_pin = "C1" *) input my_pin1;
(* altera_chip_pin_lc = "@4" *) input my_pin2; |
VHDL |
entity my_entity is
port(my_pin1: in std_logic; my_pin2: in std_logic;…);
end my_entity;
attribute chip_pin : string;
attribute altera_chip_pin_lc : string;
attribute chip_pin of my_pin1 : signal is "C1";
attribute altera_chip_pin_lc of my_pin2 : signal is "@4"; |
For bus I/O ports, the value of the chip pin attribute is a comma-delimited list of pin assignments. The order in which you declare the range of the port determines the mapping of assignments to individual bits in the port. To leave a bit unassigned, leave its corresponding pin assignment blank.
Table 59. Applying Chip Pin to a Bus of PinsThe example in this table assigns my_pin[2] to Pin_4, my_pin[1] to Pin_5, and my_pin[0] to Pin_6.
HDL |
Code |
Verilog-1995 |
input [2:0] my_pin /* synthesis chip_pin = "4, 5, 6" */; |
Table 60. Applying Chip Pin to Part of a BusThe example in this table reverses the order of the signals in the bus, assigning my_pin[0] to Pin_4 and my_pin[2] to Pin_6 but leaves my_pin[1] unassigned.
HDL |
Code |
Verilog-1995 |
input [0:2] my_pin /* synthesis chip_pin = "4, ,6" */; |
Table 61. Applying Chip Pin to Part of a Bus of PinsThe example in this table assigns my_pin[2] to Pin 4 and my_pin[0] to Pin 6, but leaves my_pin[1] unassigned.
HDL |
Code |
VHDL |
entity my_entity is
port(my_pin: in std_logic_vector(2 downto 0);…);
end my_entity;
attribute chip_pin of my_pin: signal is "4, , 6"; |
Table 62. VHDL and Verilog-2001 Examples: Assigning Pin Location and I/O Standard
HDL |
Code |
VHDL |
attribute altera_chip_pin_lc: string;
attribute altera_attribute: string;
attribute altera_chip_pin_lc of clk: signal is "B13";
attribute altera_attribute of clk:signal is "-name IO_STANDARD ""3.3-V LVCMOS"""; |
Verilog-2001 |
(* altera_attribute = "-name IO_STANDARD \"3.3-V LVCMOS\"" *)(* chip_pin = "L5" *)input clk;
(* altera_attribute = "-name IO_STANDARD LVDS" *)(* chip_pin = "L4" *)input sel;
output [3:0] data_o, input [3:0] data_i); |
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