Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.17. Disable Register Merging/Don’t Merge Register

This logic option and attribute prevents the specified register from merging with other registers and prevents other registers from merging with the specified register. When applied to a design entity, it applies to all registers in the entity.

You can set the Disable Register Merging logic option in the Quartus® Prime software, or you can set the dont_merge attribute in your HDL code, as shown in these examples. In these examples, the logic option or the attribute prevents the my_reg register from merging.

Table 21.  Setting the dont_merge attribute in HDL code
HDL Code
Verilog HD
reg my_reg /* synthesis dont_merge */;
Verilog-2001 and SystemVerilog
(* dont_merge *) reg my_reg;
signal my_reg : stdlogic;
attribute dont_merge : boolean;
attribute dont_merge of my_reg : signal is true;