- 18.104.22.168. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 22.214.171.124. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.23. Controlling Clock Enable Signals with Auto Clock Enable Replacement and direct_enable
The Auto Clock Enable Replacement logic option allows the software to find logic that feeds a register and move the logic to the register’s clock enable input port. To solve fitting or performance issues with designs that have many clock enables, you can turn off this option for individual registers or design entities. Turning the option off prevents the software from using the register’s clock enable port. The software implements the clock enable functionality using multiplexers in logic cells.
If the software does not move the specific logic to a clock enable input with the Auto Clock Enable Replacement logic option, you can instruct the software to use a direct clock enable signal. The attribute ensures that the signal drives the clock enable port, and the software does not optimize or combine the signal with other logic.
These tables show how to set this attribute to ensure that the attribute preserves the signal and uses the signal as a clock enable.
|Verilog-2001 and SystemVerilog||
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