Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.4.23. Controlling Clock Enable Signals with Auto Clock Enable Replacement and direct_enable

The Auto Clock Enable Replacement logic option allows the software to find logic that feeds a register and move the logic to the register’s clock enable input port. To solve fitting or performance issues with designs that have many clock enables, you can turn off this option for individual registers or design entities. Turning the option off prevents the software from using the register’s clock enable port. The software implements the clock enable functionality using multiplexers in logic cells.

If the software does not move the specific logic to a clock enable input with the Auto Clock Enable Replacement logic option, you can instruct the software to use a direct clock enable signal. The attribute ensures that the signal drives the clock enable port, and the software does not optimize or combine the signal with other logic.

These tables show how to set this attribute to ensure that the attribute preserves the signal and uses the signal as a clock enable.

Table 29.  Setting the direct_enable in HDL Code
HDL Code
Verilog HDL
wire my_enable /* synthesis direct_enable = 1 */ ;
attribute direct_enable: boolean;
attribute direct_enable of my_enable: signal is true;
Table 30.  Setting the syn_direct_enable in HDL CodeThe Quartus® Prime software supports the syn_direct_enable attribute name for compatibility with other synthesis tools.
HDL Code
Verilog-2001 and SystemVerilog
(* syn_direct_enable *) wire my_enable;