- 126.96.36.199. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 188.8.131.52. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
184.108.40.206. Manually Specifying State Assignments Using the syn_encoding Attribute
The Intel® Quartus® Prime software infers state machines from enumerated types and automatically assigns state encoding based on State Machine Processing.
With this logic option, you can choose the value User-Encoded to use the encoding from your HDL code. However, in standard VHDL code, you cannot specify user encoding in the state machine description because enumeration literals have no numeric values in VHDL.
To assign your own state encoding for the User-Encoded State Machine Processing setting, use the syn_encoding synthesis attribute to apply specific binary encodings to the elements of an enumerated type or to specify an encoding style. The Intel® Quartus® Prime software can implement Enumeration Types with different encoding styles, as listed in this table.
|Attribute Value||Enumeration Types|
|"default"||Use an encoding based on the number of enumeration literals in the Enumeration Type. If the number of literals is less than five, use the "sequential" encoding. If the number of literals is more than five, but fewer than 50, use a "one-hot" encoding. Otherwise, use a "gray" encoding.|
|"sequential"||Use a binary encoding in which the first enumeration literal in the Enumeration Type has encoding 0 and the second 1.|
|"gray"||Use an encoding in which the encodings for adjacent enumeration literals differ by exactly one bit. An N-bit gray code can represent 2N values.|
|"johnson"||Use an encoding similar to a gray code. An N-bit Johnson code can represent at most 2N states, but requires less logic than a gray encoding.|
|"one-hot"||The default encoding style requiring N bits, in which N is the number of enumeration literals in the Enumeration Type.|
|"compact"||Use an encoding with the fewest bits.|
|"user"||Encode each state using its value in the Verilog source. By changing the values of your state constants, you can change the encoding of your state machine.|
The syn_encoding attribute must follow the enumeration type definition, but precede its use.
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