Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Synthesis Attributes in Verilog-2001

You must use Verilog-2001 attributes as a prefix to a declaration, module item, statement, or port connection, and as a suffix to an operator or a Verilog HDL function name in an expression.

Note: Formal verification does not support the Verilog-2001 attribute syntax because the tools do not recognize the syntax.

Specifying Synthesis Attributes in Verilog-2001 and SystemVerilog

(* <attribute> [ = <value> ] *)

Applying Multiple Attributes

To apply multiple attributes to the same instance in Verilog-2001 or SystemVerilog, separate the attributes with commas.

(* <attribute1> [ = <value1>], <attribute2> [ = <value2> ] *)

For example, to set the maxfan attribute to 16 and set the preserve attribute on a register called my_reg, use the following syntax:

(* maxfan = 16, preserve *) reg my_reg;