Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Synthesis Attributes

The Quartus® Prime software supports synthesis attributes for Verilog HDL and VHDL, also commonly called pragmas. These attributes are not standard Verilog HDL or VHDL commands. Synthesis tools use attributes to control the synthesis process. The Quartus® Prime software applies the attributes in the HDL source code, and attributes always apply to a specific design element. Some synthesis attributes are also available as Quartus® Prime logic options via the Quartus® Prime software or scripting. Each attribute description indicates a corresponding setting or a logic option that you can set in the Quartus® Prime software. You can specify only some attributes with HDL synthesis attributes.

Attributes specified in your HDL code are not visible in the Assignment Editor or in the .qsf. Assignments or settings made with the Quartus® Prime software, the .qsf, or the Tcl interface take precedence over assignments or settings made with synthesis attributes in your HDL code. The Quartus® Prime software generates warning messages if the software finds invalid attributes, but does not generate an error or stop the compilation. This behavior is necessary because attributes are specific to various design tools, and attributes not recognized in the Quartus® Prime software might be for a different EDA tool. The Quartus® Prime software lists the attributes specified in your HDL code in the Source assignments table of the Analysis & Synthesis report.

The Verilog-2001, SystemVerilog, and VHDL language definitions provide specific syntax for specifying attributes, but in Verilog-1995, you must embed attribute assignments in comments. You can enter attributes in your code using the syntax in Specifying Synthesis Attributes in Verilog-1995 through Synthesis Attributes in VHDL, in which <attribute>, <attribute type>, <value>, <object>, and <object type> are variables, and the entry in brackets is optional. These examples demonstrate each syntax form.

Note: Verilog HDL is case sensitive; therefore, synthesis attributes in Verilog HDL files are also case sensitive.

In addition to the synthesis keyword shown above, the Quartus® Prime software supports the pragma, synopsys, and exemplar keywords for compatibility with other synthesis tools. The software also supports the altera keyword, which allows you to add synthesis attributes that the Quartus® Prime Integrated Synthesis feature recognizes and not by other tools that recognize the same synthesis attribute.

Note: Because formal verification tools do not recognize the exemplar, pragma, and altera keywords, avoid using these attribute keywords when using formal verification.