- 22.214.171.124. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 126.96.36.199. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
2.7.1. Creating an .sdc File with Project-Wide Constraints
The .sdc with project-wide constraints is used in the partition, but is not exported back to the top-level design. The partition designer should not modify this file. If changes are necessary, they should be communicated to the project lead, who can then update the SDC constraints and distribute new files to all partition designers as required.
The .sdc should include clock creation and clock constraints for any clock used by more than one partition. These constraints are particularly important when working with complex clocking structures, such as the following:
- Cascaded clock multiplexers
- Cascaded PLLs
- Multiple independent clocks on the same clock pin
- Redundant clocking structures required for secure applications
- Virtual clocks and generated clocks that are consistently used for source synchronous interfaces
- Clock uncertainties
Additionally, the .sdc with project-wide constraints should contain all project-wide timing exception assignments, such as the following:
- Multicycle assignments, set_multicycle_path
- False path assignments, set_false_path
- Maximum delay assignments, set_max_delay
- Minimum delay assignments, set_min_delay
The project-wide .sdc can also contain any set_input_delay or set_output_delay constraints that are used for ports in separate Intel® Quartus® Prime projects, because these represent delays external to a given partition. If the partition designer wants to set these constraints within the separate Intel® Quartus® Prime projects, the team must ensure that the I/O port names are identical in all projects so that the assignments can be integrated successfully without changes.
Similarly, a constraint on a path that crosses a partition boundary should be in the project-wide .sdc, because it is not completely localized in a separate Intel® Quartus® Prime project.
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