- 188.8.131.52. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 184.108.40.206. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
3.4.13. Power-Up Level
This logic option causes a register (flipflop) to power up with the specified logic level, either high (1) or low (0). The registers in the core hardware power up to 0 in all Altera devices. For the register to power up with a logic level high, the Compiler performs an optimization referred to as NOT-gate push back on the register. NOT-gate push back adds an inverter to the input and the output of the register, so that the reset and power-up conditions appear to be high and the device operates as expected. The register itself still powers up to 0, but the register output inverts so the signal arriving at all destinations is 1.
The Power-Up Level option supports wildcard characters, and you can apply this option to any register, registered logic cell WYSIWYG primitive, or to a design entity containing registers, if you want to set the power level for all registers in your design entity. If you assign this option to a registered logic cell WYSIWYG primitive, such as an atom primitive from a third-party synthesis tool, you must turn on the Perform WYSIWYG Primitive Resynthesis logic option for the option to take effect. You can also apply the option to a pin with the logic configurations described in the following list:
- If you turn on this option for an input pin, the option transfers to the register that the pin drives, if all these conditions are present:
- No logic, other than inversion, between the pin and the register.
- The input pin drives the data input of the register.
- The input pin does not fan-out to any other logic.
- If you turn on this option for an output or bidirectional pin, the option transfers to the register that feeds the pin, if all these conditions are present:
- No logic, other than inversion, between the register and the pin.
- The register does not fan out to any other logic.
Inferred Power-Up Levels
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