Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.2.7. Using Parameters/Generics

The Quartus® Prime software supports parameters (known as generics in VHDL) and you can pass these parameters between design languages.

Click Assignments > Settings > Compiler Settings > Default Parameters to enter default parameter values for your design. In AHDL, the Quartus® Prime software inherits parameters, so any default parameters apply to all AHDL instances in your design. You can also specify parameters for instantiated modules in a .bdf. To specify parameters in a .bdf instance, double-click the parameter value box for the instance symbol, or right-click the symbol and click Properties, and then click the Parameters tab.

You can specify parameters for instantiated modules in your design source files with the provided syntax for your chosen language. Some designs instantiate entities in a different language; for example, they might instantiate a VHDL entity from a Verilog HDL design file. You can pass parameters or generics between VHDL, Verilog HDL, AHDL, and BDF schematic entry, and from EDIF or VQM to any of these languages. You do not require an additional procedure to pass parameters from one language to another. However, sometimes you must specify the type of parameter you are passing. In those cases, you must follow certain guidelines to ensure that the Quartus® Prime software correctly interprets the parameter value.