Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents

3.8.2. Node-Naming Conventions for Registers (DFF or D Flipflop Atoms)

In Verilog HDL and VHDL, inferred registers use the names of the reg or signal connected to the output.

Table 70.  HDL Example of a Register that Creates my_dff_out DFF Primitive
HDL Register Code
Verilog HDL
wire dff_in, my_dff_out, clk;
always @ (posedge clk)
my_dff_out <= dff_in;
signal dff_in, my_dff_out, clk;
process (clk)
if (rising_edge(clk)) then
my_dff_out <= dff_in;
end if;
end process;

AHDL designs explicitly declare DFF registers rather than infer, so the software uses the user-declared name for the register.

For schematic designs using a .bdf, your design names all elements when you instantiate the elements in your design, so the software uses the name you defined for the register or DFF.

In the special case that a wire or signal (such as my_dff_out in the preceding examples) is also an output pin of your top-level design, the Quartus® Prime software cannot use that name for the register (for example, cannot use my_dff_out) because the software requires that all logic and I/O cells have unique names. Here, Quartus® Prime Integrated Synthesis appends ~reg0 to the register name.

Table 71.  Verilog HDL Register Feeding Output PinFor example, the Verilog HDL code example in this table generates a register called q~reg0.
HDL Code
Verilog HDL
module my_dff (input clk, input d, output q);
always @ (posedge clk)
q <= d;

This situation occurs only for registers driving top-level pins. If a register drives a port of a lower level of the hierarchy, the software removes the port during hierarchy flattening and the register retains its original name, in this case, q.