- 18.104.22.168. Reducing Opening a Project, Creating Design Partitions, andPerforming an Initial Compilation
- 22.214.171.124. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
1.10.13. I/O Register Packing
The following specific circumstances are required for input pin cross‑partition register packing:
- The input pin feeds exactly one register.
- The path between the input pin and register includes only input ports of partitions that have one fan-out each.
The following specific circumstances are required for output register cross-partition register packing:
- The register feeds exactly one output pin.
- The output pin is fed by only one signal.
- The path between the register and output pin includes only output ports of partitions that have one fan-out each.
Output pins with an output enable signal cannot be packed into the device I/O cell if the output enable logic is part of a different partition from the output register. To allow register packing for output pins with an output enable signal, structure your HDL code or design partition assignments so that the register and tri-state logic are defined in the same partition.
Bidirectional pins are handled in the same way as output pins with an output enable signal. If the registers that need to be packed are in the same partition as the tri-state logic, you can perform register packing.
The restrictions on tri-state logic exist because the I/O atom (device primitive) is created as part of the partition that contains tri‑state logic. If an I/O register and its tri‑state logic are contained in the same partition, the register can always be packed with tri-state logic into the I/O atom. The same cross-partition register packing restrictions also apply to I/O atoms for input and output pins. The I/O atom must feed the I/O pin directly with exactly one signal. The path between the I/O atom and the I/O pin must include only ports of partitions that have one fan-out each.
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