Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Using Constraints

If designers create Intel® Quartus® Prime assignments or timing constraints for their partitions, they must ensure that the constraints are integrated into the top-level design. If partition designers use the same top-level project framework (and design hierarchy), the constraints or Synopsys Design Constraints File (.sdc) can be easily copied or included in the top-level design. If partition designers use a separate Intel® Quartus® Prime project with a different design hierarchy, they must ensure that constraints are applied to the appropriate level of hierarchy in the top-level design, and design the .sdc for easy delivery to the project lead.

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