Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

3.1.1. Intel® Quartus® Prime Integrated Synthesis Design and Compilation Flow

Figure 33. Basic Design Flow Using Intel® Quartus® Prime Integrated Synthesis

The Intel® Quartus® Prime Integrated Synthesis design and compilation flow consists of the following steps:

  1. Create a project in the Intel® Quartus® Prime software and specify the general project information, including the top-level design entity name.
  2. Create design files in the Intel® Quartus® Prime software or with a text editor.
  3. On the Project menu, click Add/Remove Files in Project and add all design files to your Intel® Quartus® Prime project using the Files page of the Settings dialog box.
  4. Specify Compiler settings that control the compilation and optimization of your design during synthesis and fitting.
  5. Add timing constraints to specify the timing requirements.
  6. Compile your design. To synthesize your design, on the Processing menu, point to Start, and then click Start Analysis & Synthesis. To run a complete compilation flow including placement, routing, creation of a programming file, and timing analysis, click Start Compilation on the Processing menu.
  7. After obtaining synthesis and placement and routing results that meet your requirements, program or configure your Altera device.

Integrated Synthesis generates netlists that enable you to perform functional simulation or gate-level timing simulation, timing analysis, and formal verification.