Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

2.12. Document Revision History

Table 7.  Document Revision History
Date Version Changes
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0 Removed support for early timing estimate feature.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
  • Updated description of Virtual Pin assingment to clarify that assigned pins are no longer free as input pins.
June 2014 14.0.0
  • Dita conversion.
  • Removed obsolete devices content for Arria GX, Cyclone, Cyclone II, Cyclone III, Stratix, Stratix GX, Stratix II, Stratix II GX,
  • Replace Megafunction content with IP Catalog and Parameter Editor content.
November 2013 13.1.0 Removed HardCopy device information.
November 2012 12.1.0 Added Turning On Supported Cross-Boundary Optimizations.
June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0 Updated links.
December 2010 10.1.0
  • Changed to new document template.
  • Moved "Creating Floorplan Location Assignments With Tcl Commands—Excluding or Filtering Certain Device Elements (Such as RAM or DSP Blocks)" from the Intel® Quartus® Prime Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Intel® Quartus® Prime Handbook.
  • Consolidated Design Partition Planner and Incremental Compilation Advisor information between the Intel® Quartus® Prime Incremental Compilation for Hierarchical and Team-Based Design and Best Practices for Incremental Compilation Partitions and Floorplan Assignments handbook chapters.
July 2010 10.0.0
  • Removed the explanation of the “bottom-up design flow” where designers work completely independently, and replaced with Altera’s recommendations for team-based environments where partitions are developed in the same top-level project framework, plus an explanation of the bottom-up process for including independent partitions from third-party IP designers.
  • Expanded the Merge command explanation to explain how it now accommodates cross-partition boundary optimizations.
  • Restructured Altera recommendations for when to use a floorplan.
October 2009 9.1.0
  • Redefined the bottom-up design flow as team-based and reorganized previous design flow examples to include steps on how to pass top-level design information to lower-level projects.
  • Added "Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery" from the Intel® Quartus® Prime Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Intel® Quartus® Prime Handbook.
  • Reorganized the "Recommended Design Flows and Application Examples" section.
  • Removed HardCopy APEX and HardCopy Stratix Devices section.
March 2009 9.0.0
  • Added I/O register packing examples from Incremental Compilation for Hierarchical and Team-Based Designs chapter
  • Moved "Incremental Compilation Advisor" section
  • Added "Viewing Design Partition Planner and Floorplan Side-by-Side" section
  • Updated Figure 15-22
  • Chapter 8 was previously Chapter 7 in software release 8.1.
November 2008 8.1.0
  • Changed to 8-1/2 x 11 page size. No change to content.
May 2007 8.0.0
  • Initial release.