188.8.131.52. Inferred Power-Up Levels
Intel® Quartus® Prime Integrated Synthesis reads default values for registered signals defined in Verilog HDL and VHDL code, and converts the default values into Power-Up Level settings. The software also synthesizes variables with assigned values in Verilog HDL initial blocks into power-up conditions. Synthesis of these default and initial constructs allows synthesized behavior of your design to match, as closely as possible, the power-up state of the HDL code during a functional simulation.
The following register declarations all set a power-up level of VCC or a logic value “1”, as shown in this example:
signal q : std_logic = '1'; -- power-up to VCC reg q = 1'b1; // power-up to VCC reg q; initial begin q = 1'b1; end // power-up to VCC
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