Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

3.5.13. Translate Off and On / Synthesis Off and On

The translate_off and translate_on synthesis directives indicate whether the Intel® Quartus® Prime software or a third-party synthesis tool should compile a portion of HDL code that is not relevant for synthesis. The translate_off directive marks the beginning of code that the synthesis tool should ignore; the translate_on directive indicates that synthesis should resume. You can also use the synthesis_on and synthesis_off directives as a synonym for translate on and off.

You can use these directives to indicate a portion of code for simulation only. The synthesis tool reads synthesis-specific directives and processes them during synthesis; however, third-party simulation tools read the directives as comments and ignore them.

These examples show these directives.

Table 53.  Translate Off and On
HDL Code
Verilog HDL
// synthesis translate_off
parameter tpd = 2;    // Delay for simulation
#tpd;
// synthesis translate_on
VHDL
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
VHDL 2008
/* synthesis translate_off */
use std.textio.all;
/* synthesis translate_on */

If you want to ignore only a portion of code in Intel® Quartus® Prime Integrated Synthesis, you can use the Altera-specific attribute keyword altera. For example, use the // altera translate_off and // altera translate_on directives to direct Intel® Quartus® Prime Integrated Synthesis to ignore a portion of code that you intend only for other synthesis tools.

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