Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Document Table of Contents Synthesis and Fitting Optimizations

Logic optimization during synthesis might remove registers if you do not connect the registers to inputs or outputs in your design, or if you can simplify the logic due to constant signal values. Synthesis optimizations might change register names, such as when the software merges duplicate registers to reduce resource utilization.

NOT-gate push back optimizations can affect registers that use preset signals. This type of optimization can impact your timing assignments when the software uses registers as clock dividers. If this situation occurs in your design, change the clock settings to work on the new register name.

Synthesis netlist optimizations often change node names because the software can combine or duplicate registers to optimize your design.

The Quartus® Prime Compilation Report provides a list of registers that synthesis optimizations remove, and a brief reason for the removal. To generate the Quartus® Prime Compilation Report, follow these steps:

  1. In the Analysis & Synthesis folder, open Optimization Results.
  2. Open Register Statistics, and then click the Registers Removed During Synthesis report.
  3. Click Removed Registers Triggering Further Register Optimizations.

The second report contains a list of registers that causes synthesis optimizations to remove other registers from your design. The report provides a brief reason for the removal, and a list of registers that synthesis optimizations remove due to the removal of the initial register.

Quartus® Prime Integrated Synthesis creates synonyms for registers duplicated with the Maximum Fan-Out option (or maxfan attribute). Therefore, timing assignments applied to nodes that are duplicated with this option are applied to the new nodes as well.

The Quartus® Prime Fitter can also change node names after synthesis (for example, when the Fitter uses register packing to pack a register into an I/O element, or when physical synthesis modifies logic). The Fitter creates synonyms for duplicated registers so timing analysis can use the existing node name when applying assignments.

You can instruct the Quartus® Prime software to preserve certain nodes throughout compilation so you can use them for verification or making assignments.