Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents Setting a Verilog HDL Macro Default Value on the Command Line

To set a default value for a Verilog HDL macro on the command line, use the --verilog_macro option:

quartus_map <Design name> --verilog_macro= "<Macro name>=<Macro setting>" 

The command in this example has the same effect as specifying 
`define a 2 in the Verilog HDL source code:

quartus_map my_design --verilog_macro="a=2"

To specify multiple macros, you can repeat the option more than once.

quartus_map my_design --verilog_macro="a=2" --verilog_macro="b=3"